The present invention generally relates to semiconductor devices and more particularly to a probe card and testing method suitable for use with a high-speed semiconductor device operating with a clock rate of 1 GHz or more. Further, the present invention relates to a capacitor used for a decoupling capacitor of a high-speed semiconductor device and manufacturing method thereof.
Conventionally, probe cards have been used for testing electric properties and circuit functions of semiconductor chips formed on a semiconductor wafer. Typically, the testing is conducted in the state the semiconductor chips are still in the form of a wafer, and the probe card is urged against the wafer so that probes provided on the probe card make a contact with corresponding electrode pads on the semiconductor chip. Thereby, the probe card provides interconnection between the semiconductor chip and a testing apparatus to which the probe card is connected, by means of the probes and an interconnection structure provided on the probe card.
For example, Japanese Laid-Open Patent Application 6-140048 discloses such a probe card formed of a ceramic substrate carrying thereon a wiring pattern. In this conventional probe card, contact pads provided on the wiring pattern make a contact with corresponding electrode pads on the semiconductor device, and the interconnection pattern provides electrical connection between the foregoing contact pads. Further, input/output electrode pads are provided on the probe card for in and out of probe signals. Further, the foregoing interconnection pattern forms a thin film resistor or capacitor on the ceramic substrate and achieves impedance control and cutoff of power-line noise.
Japanese Laid-Open Patent Application 7-111280 discloses another probe card that carries a plurality of probes at a rear surface of the probe card. In this construction, the interconnection pattern is provided on the front surface, and various exterior circuit parts such as bypass capacitors or wave-shaping circuits are connected to this interconnection pattern at the front side of the probe card substrate. Such a construction of providing the probes and exotic circuit components at different sides of the probe card substrate makes it possible to dispose the exotic circuit components immediately adjacent to the probes. Thereby, the accuracy of testing is improved.
Japanese Laid-Open Patent Application 10-132855 discloses a probe card in which probes for contacting with a semiconductor device to be tested are provided on a multilayer circuit board at a first side thereof and chip components such as inductors, capacitors, resistors, and the like, that can form an electric circuit together with the semiconductor device, are provided on a second side of the multilayer circuit board. By using such a probe card, it becomes possible to conduct the test of the semiconductor chip in the state close to the case in which the semiconductor chip is actually used, and the accuracy of the test is improved.
Further, Japanese Laid-Open Patent Application 2000-304770 discloses a probe card in which a build-up interconnection structure is formed on a support substrate and a plurality of probes are formed on the uppermost layer of the build-up interconnection structure. By using the build-up interconnection structure, it becomes possible to realize intricate and complex wiring, thus allowing a highly dense arrangement of the probes.
Japanese Laid-Open Patent Application 2001-102418 provides a probe device in which a detachable contactor, formed of a ceramic substrate carrying probes thereon, is connected to a pin-electronic package via an interposer, and the structure thus formed is mounted on a circuit board. In this reference, the pin-electronic package includes various circuits such as drivers, comparators, and dynamic loaders. Further, the pin-electronic package may include a cooling device in view of severe heating caused by these circuits.
Meanwhile, in the testing process of recent high-speed semiconductor devices, which generally have a very large number of terminals, there is a demand for a probe card that the probes are provided with large density in correspondence to the electrode pads formed on the semiconductor chip with high density and further that a decoupling capacitor is provided immediately adjacent to the probes for effectively suppressing the high-frequency noise.
With regard to the semiconductor device, there has been developed recently a semiconductor package for a ultrahigh speed semiconductor chip operable at the clock rate of 1 GHz or more. In such a semiconductor package, a semiconductor chip and a capacitor are mounted at respective sides of a build-up substrate, wherein a very thin build-up substrate having a thickness of 1 mm or less is generally used for minimizing the inductance between the semiconductor chip and the capacitor.
Further, there is proposed a new process of forming an extremely thin build-up substrate directly on an LSI chip to form a BBUL (bumpless build-up layer) structure (Nikkei Microdevices, December 2001, pp. 178), wherein this BBUL structure provides a decoupling capacitor on the uppermost layer of the build-up substrate formed on the LSI chip in electrical connection with the LSI chip via the build-up substrate.
In such ultrahigh-speed semiconductor devices, meaningful test can be achieved only when the decoupling capacitor is provided immediately adjacent to the semiconductor chip to be tested so that the semiconductor chip to be tested operates just in the same way as it is actually used during the test.
Conventionally, there has been no probe card that can satisfy such a demand.
In the case of the probe card of Japanese Laid-Open Patent Application 2000-304770, for example, it can certainly test a semiconductor chip having a large number of contact terminals arranged in high density by providing the probes on the probe card substrate with corresponding high density. However, such a construction provides a very narrow gap between the probe card and the semiconductor chip, and there is no choice but to provide the decoupling capacitor at the rear side of the probe card substrate, just as in the case of Japanese Laid-Open Patent Application 10-132855. On the other hand, the substrate of a probe card for testing high-speed semiconductor chips generally has a thickness of 3–5 mm in view of the need of carrying complex wiring patterns and in view of the need of having a sufficient rigidity, which is required for achieving uniform contact when the probes are urged to a semiconductor chip at the time of testing.
In the construction of the Japanese Laid-Open Patent Application 10-132855, in particular, the wiring length for the interconnection between the capacitor component provided at the rear side of the multilayer substrate and the electrodes of the semiconductor chip to be tested becomes as large as about 6 mm. Thereby, the inductance associated with the long interconnection causes a problem that the capacitor cannot cut off the high-frequency noise effectively when the semiconductor chip is operated at high speed during the test.
Meanwhile, there is a demand also in recent ultrahigh-speed and ultra low-power semiconductor devices and LSIs, such as microprocessors, to suppress the fluctuation of the supply voltage while it is operated by cutting the switching noise so that a stable device operation is maintained even when there has been caused a sudden change of the load.
In view of such a demand, it has been practiced to provide a decoupling capacitor in the vicinity of a semiconductor chip for absorbing the high-frequency noise such as switching noise.
On the other hand, such a construction generally uses a wiring pattern for connecting the semiconductor device to the decoupling captor, and thus, there arises the problem that the inductance associated with such a wiring pattern causes the problem that the effectiveness of the decoupling capacitor of cutting the high-frequency noise is degraded seriously.
In order to avoid this problem, there has been a proposal to construct the decoupling capacitor in the form of an interposer. Thereby, the capacitor configured in the form of an interposer is disposed right underneath the semiconductor chip, and the wiring length between the capacitor and the semiconductor chip is minimized.
FIGS. 1A and 1B show the construction of a semiconductor device 100 having an interposer-type decoupling capacitor.
Referring to FIG. 1A, the semiconductor device 100 has a construction in which an interposer-type decoupling capacitor 102 is mounted upon a semiconductor chip by way of bumps 103A. Further, the decoupling capacitor 102 thus carrying the semiconductor chip 101 thereon is mounted on a package substrate 104 by way of bumps 103B. Further, the package substrate 104 thus carrying thereon the decoupling capacitor 102 and the semiconductor chip 101 is mounted on a circuit substrate 105 by way of bumps 106.
By using the interposer-type decoupling capacitor 102, the wiring length from the semiconductor chip 101 to the decoupling capacitor 102 becomes minimum, and elimination of high-frequency noise can be achieved effectively.
The construction of FIG. 1A can also be modified as represented in FIG. 1B, wherein FIG. 1B shows a semiconductor device 100A that uses a package substrate 104A in place of the package substrate 104. As can be seen, the package substrate 104A has a depression. In FIG. 1B, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
By accommodating the interposer-type decoupling capacitor 102 into such a depression, the construction of FIG. 1B can reduce the distance between the semiconductor chip 101 and the circuit substrate 105.
Such an interposer-type decoupling capacitor is generally formed on a substrate having a flat and smooth surface.
FIGS. 2A–2D show a part of the process of forming such a conventional interposer-type decoupling capacitor.
Referring to the drawings, the decoupling capacitor uses a silicon substrate 201 shown in FIG. 2A and forms a lower electrode 202 on the silicon substrate 201 as represented in FIG. 2B.
Next, as represented in FIG. 2C, a dielectric film 203 is formed on the lower electrode and an upper electrode 204 is formed on the dielectric layer 203 in the step of FIG. 2D.
After the step of FIG. 2D, the laminated structure of FIG. 2D is subjected to a process of forming through-holes such that the through-holes penetrate through the silicon substrate from a first side to a second, opposite side, while such a process of forming the through-holes takes substantial time, and the cost of the interposer-type decoupling capacitor is increased as a result. Further, there is a need of providing an interconnection pattern including the process of forming via-holes during the process of forming the interposer-type decoupling capacitor.
As noted above, the problem of using the interposer-type decoupling capacitor such as the one shown in FIG. 1A is that the distance between the bottom surface of the semiconductor chip 101 and the top surface of the package substrate 104, and hence the distance between the bottom surface of the semiconductor chip 101 and the top surface of the circuit substrate 105, is increased as a result of the use of the interposer-type decoupling capacitor 102. While the construction of FIG. 1B reduces this problem to some extent, the use of the interposer-type decoupling capacitor nevertheless raises the problem of increased distance between the semiconductor chip 101 and the circuit substrate 105 and associated problem of increase of inductance.